Dynamic random access memory integrated circuits (DRAM IC's) undergo testing by the manufacturer during production and often by the end user, for example, in a memory test conducted during computer initialization. As DRAM IC densities increase, so that individual DRAM IC's are capable of storing four or more megabits of information, the time necessary for testing the IC's increases as well. To reduce the testing time required, it is known in the art to place the DRAM IC's in a test mode for that purpose, as distinguished from the normal operating mode. In a normal operating mode, a DRAM IC reads and writes one bit at a time. A DRAM IC could be tested in the normal operating mode, but the time required to conduct exhaustive testing is excessive.
In a test mode, multiple memory cell bits or words in the DRAM IC are tested simultaneously, thus reducing test time. In a four megabit DRAM, for example, the DRAM can be internally organized as 4,914,304 words by one bit. In the test mode, data (ones or zeros) can be written into eight sectors in parallel and retrieved in the same way. If, upon reading, all bits are equal (all ones or all zeros), the data output pin (DQ) indicates a one. If any of the bits differed, the data output pin would indicate a zero. In test mode, therefore, the 4M DRAM can be tested as if it were a 512K DRAM, thereby reducing the testing time.
Switching a DRAM IC into test mode can be accomplished by using a combination of input signals that would not be encountered in normal operation. For example, a DRAM can be switched into test mode by inserting WRITE* and CAS* signals before RAS* (WCBR) cycle (where an asterisk indicates a complement or active low signal). Reset is done by a sequence of CAS* before RAS* refresh (CBRR) cycle or RAS* only refresh (ROR) cycle, thereby returning the device to the normal operating mode.
It is also known to switch a DRAM IC device into test mode by using a supervoltage technique. A test function voltage is applied to one of the IC pins (typically called TE, or test mode enable), to trigger the device into a test mode. A typical test function voltage is 4.5 volts higher than the chip supply voltage (Vcc).
But there is a problem using the multiple bit test method, that is, if by chance all of the eight bits were in the wrong state, the output pin would still indicate one since all bits are the same. Therefore, the test is not valid.
This is also a problem with the Joint Electronic Device Engineering Council (JEDEC) Standard 21-C, "DRAM Special Test and Operational Modes", which uses the WCBR cycle to activate special modes. The particular mode is selected by the use of the lower order (A0-A7) address line coding, i.e., A6*, A5*, and A7* to select a JEDEC "registered" test mode, and A6*, A5, and A7* to select a "registered" JEDEC operational mode. A vendor or customer specific mode is selected by A6, A5*, and A7. A0-A4 input signals are used to further define the individual modes within a block.